1. Field of the Invention
The present invention relates to a method of manufacturing a contact structure and more particularly to formation of a buried wiring and a low dielectric constant interlayer insulating film.
2. Description of the Background Art
In order to implement an increase in a speed in a semiconductor device having a small gate length (0.18 xcexcm or less, for example), it is important that a signal delay in the device should be reduced. The signal delay in the device is represented by the sum of a signal delay in a transistor and a signal delay in a wiring. As a reduction in a wiring pitch is advanced rapidly, the signal delay in the wiring occupies a greater part of the signal delay in the device than the signal delay in the transistor.
The signal delay in the wiring is proportional to a product of a resistance of the wiring and a capacitance between the wirings. Therefore, it is necessary to decrease the resistance of the wiring or the capacitance between the wirings, thereby reducing the signal delay in the wiring. In order to solve this problem, there has vigorously been studied a combination of a buried wiring technique using a metal having a low resistance such as copper and a technique for forming an interlayer insulating film having a lower dielectric constant than that of a silicon oxide film to be a conventional typical interlayer insulating film. The present invention relates to a method of manufacturing a contact structure having a combination of a buried wiring forming method (a so-called Dual Damascene process) of forming a connecting hole for a lower layer wiring and an upper layer wiring at a time and formation of an organic low dielectric constant interlayer insulating film.
FIGS. 7 to 19 typically show each step of a conventional method of manufacturing a contact structure in which the formation of the buried wiring and that of the low dielectric constant interlayer insulating film are combined. FIGS. 14 to 17 are single view drawings for easily distinguishing a connecting hole from a wiring trench.
As shown in FIG. 7, first of all, an element such as a transistor is formed on a semiconductor substrate 1 such as a silicon substrate, and an insulating film is then formed to cover the element. In FIG. 7, the element and the insulating film are collectively represented as a lower insulating layer 2 and the element is not shown.
Next, a first low dielectric constant interlayer insulating film 3 is formed on the lower insulating layer 2, and a hard mask 4 is formed on the first low dielectric constant interlayer insulating film 3. A polyarylether (hereinafter referred to as PAE) film to be an organic substance comprising carbon, oxygen and hydrogen as main components, for example, is employed as the first low dielectric constant interlayer insulating film 3 and a silicon oxide film is employed as the hard mask 4, for example.
A photoresist 16 is formed on the hard mask 4 and a pattern 17a of the wiring trench is formed by using a photolithographic technique (FIG. 8). Then, the hard mask 4 is subjected to etching by using the photoresist 16 as a mask so that a pattern 17b of the wiring trench is formed in the hard mask 4 (FIG. 9). In the case in which the silicon oxide film is employed as the hard mask 4, etching is carried out through plasma etching using a mixed gas of CF4 and O2, for example.
After the etching for the hard mark 4 is completed, the first low dielectric constant interlayer insulating film 3 is subjected to the etching to form a wiring trench 17c. In the case in which the PAE film is employed as the first low dielectric constant interlayer insulating film 3, plasma etching using a mixed gas of O2 and N2 is carried out, for example. An etching gas has an etching effect for the photoresist. Therefore, the photoresist 16 can also be removed at the same time that the first low dielectric constant interlayer insulating film 3 is to be etched (FIG. 10). In this case, the hard mask 4 prevents the first low dielectric constant interlayer insulating film 3 in a portion other than an opening of the pattern 17b from being etched after the photoresist 16 is completely removed. For example, since the silicon oxide film is not removed by the plasma etching using the mixed gas of O2 and N2, it is suitable for the hard mask 4.
Then, a barrier metal (not shown) is formed over the whole surface of the semiconductor substrate 1 by using a sputtering method, for example, and a first metal film 5 such as copper is formed on the barrier metal by using the sputtering method, a chemical vapor deposition (hereinafter referred to as CVD) process, an electrolytic plating method or the like (FIG. 11), for example. The barrier metal is provided to prevent a metal constituting the first metal film 5 from being diffused into the lower insulating layer 2 and the first low dielectric constant interlayer insulating film 3.
Then, the barrier metal and the first metal film 5 which are provided above a surface of the hard mark 4 are removed by using a chemical mechanical polishing (which will be hereinafter referred to as CMP) process, for example. The barrier metal and the first metal film 5 are caused to remain only in the wiring trench (FIG. 12).
Next, a first interlayer insulating film 6, a second low dielectric constant interlayer insulating film 7, a second interlayer insulating film 8, a third low dielectric constant interlayer insulating film 9 and a third interlayer insulating film 10 are formed on the hard mask 4 and the first metal film 5 in this order (FIG. 13). For example, a silicon nitride film is employed as the first interlayer insulating film 6, a silicon oxide film is employed as the second and third interlayer insulating films 8 and 10, and a PAE film is employed as the second and third low dielectric constant interlayer insulating films 7 and 9.
Subsequently, a photoresist 18 is formed on the third interlayer insulating film 10 and a pattern 15e of a connecting hole is formed in the photoresist 18 by the photolithographic technique (FIG. 14). Then, the third interlayer insulating film 10, the third low dielectric constant interlayer insulating film 9, the second interlayer insulating film 8 and the second low dielectric constant interlayer insulating film 7 are subjected to etching by using the photoresist 18 as a mask so that a connecting hole 15f is formed (FIG. 15). In the case in which the silicon oxide film is employed as the second and third interlayer insulating films 8 and 10 and the PAE film is employed as the second and third low dielectric constant interlayer insulating films 7 and 9, it is preferable that the silicon oxide film should be subjected to the plasma etching using the mixed gas of CF4 and O2 and the PAE film should be subjected to the plasma etching using the mixed gas of O2 and N2. Moreover, the photoresist 18 is removed at the same time that the PAE film is etched. Furthermore, the first interlayer insulating film 6 functions as an etching stopper during the formation of the connecting hole 15f. Accordingly, the first metal film 5 is not etched.
Next, a wiring trench is formed in the third low dielectric constant interlayer insulating film 9. For this purpose, a photoresist 19 is formed on the third interlayer insulating film 10 and a pattern 13d of the wiring trench is formed by the photolithographic technique (FIG. 16). Then, the third interlayer insulating film 10 and the third low dielectric constant interlayer insulating film 9 are subjected to etching by using the photoresist 19 as a mask so that a pattern 13e of the wiring trench is formed. Subsequently, the first interlayer insulating film 6 is subjected to the etching so that a pattern 15g of the connecting hole is formed (FIG. 17). Then, a barrier metal (not shown) is formed over the whole surface of the semiconductor substrate 1 by using a sputtering method, for example, and a second metal film 20 is formed on the barrier metal (FIG. 18). Thereafter, the barrier metal and the second metal film 20 which are provided above a surface of the third interlayer insulating film 10 are removed by using the CMP method, for example, and the barrier metal and the second metal film 20 are caused to remain only in the wiring trench 13e and the connecting hole 15g (FIG. 19).
In the case in which a photomask to be used for the patterning of the photoresists 18 and 19 has a low alignment accuracy, a pattern cannot be formed in the photoresist as designed in some cases. In those cases, the photoresist is removed and is then reformed again. Thus, the photoresist is subjected to the patterning again. At this time, the incompletely formed photoresist can be removed through plasma ashing using an O2 gas.
In the case in which the photoresist 18 is to be removed, it is sufficient that a new photoresist is formed and subjected to the patterning again. Therefore, there is no problem. However, a problem arises when the photoresist 19 is to be removed.
Since the connecting hole 15f has already been formed in the stage in which the photoresist 19 is to be removed, the second and third low dielectric constant interlayer insulating films 7 and 9 are exposed to the connecting hole 15f. Consequently, wall surfaces of the second and third low dielectric constant interlayer insulating films 7 and 9 which are exposed to the connecting hole 15f are exposed to an O2 gas plasma for removing the photoresist 19. The PAE film or the like included in the low dielectric constant interlayer insulating films has such a property that it is etched through exposure to the O2 gas plasma. Accordingly, in the case in which a material to be easily etched by the O2 gas plasma, for example, the PAE film is employed as the second and third low dielectric constant interlayer insulating films 7 and 9, a wall surface 21 exposed to the connecting hole 15f of the second and third low dielectric constant interlayer insulating films 7 and 9 is excessively etched as shown in FIG. 20 so that it retreats to a wall surface 22 in a position which is more recessed. In other words, a diameter of the connecting hole 15f is increased, resulting in an abnormal shape. Thus, such a dimension as to be designed cannot be obtained.
Consequently, the metal film cannot fully be buried in the connecting hole 15f so that a contact of the lower layer wiring with the first metal film 5 cannot be obtained sufficiently or a short-circuit is caused due to the adjacent connecting holes coupled to each other.
Moreover, also in the case in which the photomask has a high alignment accuracy and patterns are formed in the photoresists 18 and 19 as designed, the diameter of the connecting hole 15f is similarly increased easily in the stage of forming the wiring trench 13e after the state shown in FIG. 16. In order to form the wiring trench 13e, it is necessary to carry out the patterning into the third interlayer insulating film 10 and the third low dielectric constant interlayer insulating film 9. However, the connecting hole 15f has already been formed when the patterning is to be carried out. Therefore, the wall surface of the second low dielectric constant interlayer insulating film 7 which is exposed into the connecting hole 15f is easily subjected to excessive etching. More specifically, the wall surface 21 of the second low dielectric constant interlayer insulating film 7 which is exposed into the connecting hole 15f retreats to the wall surface 22 which is more recessed as shown in FIG. 21. In the same manner as the above-mentioned case, the diameter of the connecting hole 15f is increased, resulting in an abnormal shape. As a result, there is a problem in that the metal film cannot fully be buried in the connecting hole 15f or the adjacent connecting holes are short-circuited as described above.
Furthermore, the above-mentioned excessive etching for the low dielectric constant interlayer insulating film is accelerated because the surface of the third interlayer insulating film 10 is exposed during the etching of the low dielectric constant interlayer insulating film. When the photoresist 18 is completely removed from the step shown in FIG. 14 to the step shown in FIG. 15, the third interlayer insulating film 10 acts as a mask for the subsequent etching plasma. If the silicon oxide film is employed as the third interlayer insulating film 10, oxygen atoms are turned out from the surface of the silicon oxide film by the etching plasma. As a result, it is supposed that an etching plasma rich in oxygen can be generated.
In order to solve the above-mentioned problem, it is an object of the present invention to implement a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole formed in the low dielectric constant interlayer insulating film does not turn into an abnormal shape.
A first aspect of the present invention is directed to a method of manufacturing a contact structure comprising the steps of (a) preparing a substrate layer having an electrode to be connected in a surface, (b) forming a first insulating film, a second insulating film, a third insulating film, a fourth insulating film having a higher tolerance to a photoresist removing processing than the third insulating film, and a fifth insulating film having a first through hole on the substrate layer in this order, (c) forming the photoresist on the fourth and fifth insulating films, patterning the photoresist, etching the fourth insulating film by using the photoresist as a mask, thereby forming, in the fourth insulating film, a second through hole partially exposed to the first through hole, (d) etching the third insulating film by using the fourth insulating film as a mask, thereby forming, in the third insulating film, a third through hole having the same shape as that of the second through hole, (e) etching the fourth insulating film by using the fifth insulating film as a mask, thereby forming a fourth through hole having the same shape as that of the first through hole, (f) etching the second insulating film by using the third insulating film as a mask, thereby forming a fifth through hole having the same shape as that of the second through hole, and (g) etching the third insulating film and the first insulating film by using the fourth insulating film and the second insulating film as masks, thereby forming sixth and seventh through holes having the same shapes as those of the first through hole and the second through hole to be positioned above the electrode, respectively.
A second aspect of the present invention is directed to the method of manufacturing a contact structure according to the first aspect of the present invention, wherein the sixth through hole and the seventh through hole are simultaneously formed at the step (g).
A third aspect of the present invention is directed to the method of manufacturing a contact structure according to the first or second aspect of the present invention, wherein the steps (e) and (f) are carried out at the same time.
A fourth aspect of the present invention is directed to the method of manufacturing a contact structure according to any of the first to third aspects of the present invention, further comprising the step (h) of removing the fifth insulating film after the step (g).
A fifth aspect of the present invention is directed to the method of manufacturing a contact structure according to any of the first to fourth aspects of the present invention, further comprising the step (i) of forming a sixth insulating film having etching selectivity to the first insulating film on the substrate layer before the step (b), and the step (j) of etching the sixth insulating film by using the first insulating film as a mask, thereby forming an eighth through hole having the same shape as that of the second through hole.
A sixth aspect of the present invention is directed to the method of manufacturing a contact structure according to the fifth aspect of the present invention, further comprising the step (h) and the step (j) are carried out at the same time.
A seventh aspect of the present invention is directed to the method of manufacturing a contact structure according to any of the first to sixth aspects of the present invention, wherein the fifth insulating film is a silicon nitride film, a silicon carbide film or a silicon carbide oxide film.
An eighth aspect of the present invention is directed to the method of manufacturing a contact structure according to any of the first to seventh aspects of the present invention, wherein the first or third insulating film is a polyarylether film, and the third, sixth or seventh through hole is formed on the first or third insulating film by plasma etching using a mixed gas of nitrogen, hydrogen and ammonia at the step (d) or (g).
According to the first aspect of the present invention, it is possible to form a contact structure in which the sixth through hole is provided in the upper side and the seventh through hole is provided in the lower side. Moreover, even if the photoresist removing processing is carried out for re-patterning during the formation of the second through hole, the third insulating film is not affected because of the existence of the fourth insulating film having a high tolerance to the photoresist removing processing.
According to the second aspect of the present invention, the formation of the sixth through hole in the third insulating film and that of the seventh through hole in the first insulating film are carried out at the same time. Therefore, it is possible to prevent the seventh through hole from being excessively etched by adjusting the materials, thicknesses and etching rates of the first and third insulating films. Accordingly, the abnormal shape of the seventh through hole is generated with difficulty.
According to the third aspect of the present invention, a short time is required for the step.
According to the fourth aspect of the present invention, the fifth insulating film is finally removed. Therefore, it is possible to use a material having a high dielectric constant for the fifth insulating film.
According to the fifth aspect of the present invention, the sixth insulating film functions as an etching stopper when the first insulating film is to be etched. Therefore, the electrode to be connected is not etched.
According to the sixth aspect of the present invention, a short time is required for the step.
According to the seventh aspect of the present invention, it is possible to suppress the acceleration of the etching of the first or third insulating film.
According to the eighth aspect of the present invention, the etching speed of the first or third insulating film is increased.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.